Synthesis of counter-multiplexer-based timing units applied in application specific DSP-ICs

Abstract

The paper is intended to present a synthesis method and its implementationthat can be used for automated designing of the timers of application-specificDSP circuits. One of the authors participated in the RT and logical level designof a CNN based image processor IC, and the intention to develop a synthesisprogramme arose from the experiments of this work. The peculiarity of thesetimers is that their state-graph consists of nested cycles. The constituents arecounters of diverse modulo-values and multiplexers, besides gate elementsused for connecting. The synthesis process proposed here starts from a verysimple specification, and generates a structural VHDL description.