Dual-Rail Asynchronous Implementation of a VLSI Processor for Digital Cellular Neural Networks

Authors

  • P. Keresztes
  • T. Hídvégi

Keywords:

emulated digital CNN-UM, clockless processors, Dual-rail logic, self-synchronization, delay-insensitive logic systems

Abstract

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Author Biographies

P. Keresztes

T. Hídvégi

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Published

2008-01-01

How to Cite

Keresztes, P., & Hídvégi, T. (2008). Dual-Rail Asynchronous Implementation of a VLSI Processor for Digital Cellular Neural Networks. Acta Technica Jaurinensis, 1(3), pp. 499–512. Retrieved from https://acta.sze.hu/index.php/acta/article/view/292

Issue

Vol. 1 No. 3 (2008)

Section

Information Technology and Electrical Engineering