Reconfigurable Mixed-Signal Neural Network with Embedded Visual Sensing

Abstract

In this paper, the architecture of a reconfigurable neural network implemented with mixed-signal VLSI hardware is presented. The proposed architecture provides a test substrate for mixed-signal hardware neuro-computing in the area of visual processing. This design consists of a reconfigurable Artificial Neural Network (ANN) utilized as a more general-purpose visual processor with a 352 x 288 photodetecting sensor array, analog RAM, and off chip sensory signal processing capability. The CMOS sensor array possesses high performance readout circuitry and embedded data storage capability. For further compactness, a new template memory structure is built that requires about quarter of silicon size compared to previous designs. The VLSI chip comprises most of the modules of a sensory system and keeps tight relationship between the sensors and the processing neural network.